题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
    reg [2:0] cnt;
    reg clk_out5_r;

    always @(posedge clk_in or negedge rst) begin
        if(rst == 1'b0)
            cnt <= 3'd0;
        else if(cnt == 3'd4)
            cnt <= 3'd0;
        else
            cnt <= cnt + 1'b1;
    end

   //always @(posedge clk_in or negedge rst) begin
   //    if(rst == 1'b0)
   //        clk_out5_r <= 1'b0;
   //    else if(cnt == 3'd2 || cnt == 3'd0)
   //        clk_out5_r <= ~clk_out5_r;
   //    else
   //        clk_out5_r <= clk_out5_r;
   //end

    always @(posedge clk_in or negedge rst) begin
        if(rst == 1'b0)
            clk_out5_r <= 1'b0;
        else if(cnt == 3'd0)
            clk_out5_r <= 1'b1;
        else if(cnt == 3'd2)
            clk_out5_r <= 1'b0;
        else
            clk_out5_r <= clk_out5_r;
    end

    assign clk_out5 = clk_out5_r;


//*************code***********//
endmodule