题解 | #根据状态转移图实现时序电路#

这一题很明显采用三段式状态机进行编写，需要注意的是第三段需要使用组合逻辑，而不能使用时序逻辑，采用时序逻辑会报错，错误显示，输出要和输入同时变化，所以需要组合逻辑
`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
    
    localparam    Zero = 2'b00;
    localparam    One  = 2'b01;
    localparam    Two  = 2'b10;
    localparam    Thre = 2'b11;
    
    reg    [1:0]    cur_state;
    reg    [1:0]    nex_state;
    
    reg    Y_temp;
    
    assign Y = Y_temp;
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            cur_state <= Zero;
        else
            cur_state <= nex_state;
    end
    
    always@(*)
    begin
        nex_state = Zero;
        case(cur_state)
            Zero    :    begin
                if(C)
                    nex_state = One;
                else
                    nex_state = Zero;
                end
            One     :    begin
                if(C)
                    nex_state = One;
                else
                    nex_state = Thre;
                end
            Two     :    begin
                if(C)
                    nex_state = Two;
                else
                    nex_state = Zero;
                end
            Thre    :    begin
                if(C)
                    nex_state = Two;
                else
                    nex_state = Thre;
                end
            default :    nex_state = Zero;
        endcase
    end
    
    always@(*)        //这里需要注意的是，我们之前都是写的时序逻辑，而此题需要写组合逻辑，因为在报错中我们可以看到，其要求的是在C变化时，输出直接就变化，没有时序的采样过程
    begin
        if(!rst_n)
            Y_temp <= 1'b0;
        else
            begin
                case(cur_state)  
                    Zero    :    begin
                        Y_temp <= 1'b0;
                        end
                    One     :    begin
                        Y_temp <= 1'b0;
                        end
                    Two     :    begin
                        if(C)
                            Y_temp <= 1'b1;
                        else
                            Y_temp <= 1'b0;
                        end
                    Thre    :    begin
                        Y_temp <= 1'b1;
                        end
                    default :    Y_temp <= 1'b0;
                endcase
            end
    end
    
    
    
endmodule