题解 | #游戏机计费程序#

`timescale 1ns/1ns module huawei5( input wire clk , input wire rst , input wire [3:0]d , output reg valid_in , output wire dout );

//**code//

reg [2:0]cnt;
reg [3:0] data;
always@(posedge clk,negedge rst)
    if(!rst)
        cnt <= 'd0;
    else if(cnt == 3'd3)
        cnt <= 3'd0;
    else
        cnt <= cnt +3'd1;

always@(posedge clk,negedge rst)
    if(!rst)
        begin
            valid_in <= 0;
            data     <= 'd0;
        end
else if(cnt == 3'd3)
    begin
        data     <= d;
        valid_in <= 1;
    end
else
     begin
        data     <= data;
        valid_in <= 0;
    end
    
assign dout = data[3-cnt];

endmodule