题解 | #同步FIFO#

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

output reg				wfull	,
output reg				rempty	,
output wire [WIDTH-1:0]	rdata
);

reg   [$clog2(DEPTH)-1:0] waddr; 
reg   [$clog2(DEPTH)-1:0] raddr;
reg   [$clog2(DEPTH):0]   cnt  ;

always@(posedge clk or negedge rst_n)begin 
    if(~rst_n)begin
       waddr <= 0; 
    end
    else    if((winc) && (~wfull))begin 
       waddr <= waddr + 1'b1; 
    end
    else    begin 
        waddr <= waddr;
    end
end

always@(posedge clk or negedge rst_n)begin 
    if(~rst_n)begin
       raddr <= 0; 
    end
    else    if((rinc) && (~rempty))begin 
       raddr <= raddr + 1'b1; 
    end
    else    begin 
       raddr <= raddr; 
    end
end

always@(posedge clk or negedge rst_n)begin 
    if(~rst_n)begin 
       cnt <= 0; 
    end
    else    if((rinc) && (~rempty) && (winc) && (~wfull))begin 
       cnt <= cnt; 
    end
    else    if((rinc) && (~rempty))begin 
       cnt <= cnt - 1'b1; 
    end
    else    if((winc) && (~wfull))begin 
       cnt <= cnt + 1'b1; 
    end
    else    begin 
       cnt <= cnt; 
    end
end

always@(posedge clk or negedge rst_n)begin 
    if(~rst_n)begin 
        wfull <= 0;
    end
    else    if(cnt == DEPTH)begin 
        wfull <= 1'b1;
    end
    else    begin 
       wfull <= 1'b0; 
    end
end

always@(posedge clk or negedge rst_n)begin 
    if(~rst_n)begin 
       rempty <= 0; 
    end
    else    if(cnt == 1'b0)begin 
       rempty <= 1'b1; 
    end
    else    begin 
       rempty <= 1'b0; 
    end
end

dual_port_RAM
#(.DEPTH (DEPTH) ,
  .WIDTH (WIDTH) 
)
dual_port_RAM_inst
(
    .wclk  (clk)          ,          
    .wenc  (winc&~wfull)  ,                    
    .waddr (waddr)        ,//深度对2取对数，得到地址的位宽。
    .wdata (wdata)        ,//数据写入
    .rclk  (clk)          ,            
    .renc  (rinc&~rempty) ,                     
    .raddr (raddr)        ,//深度对2取对数，得到地址的位宽。
    .rdata (rdata)         //数据输出
);
endmodule