题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
input clk,
input rst_n,

input write_en,
input [7:0]write_addr,
input [3:0]write_data,

input read_en,
input [7:0]read_addr,
output reg [3:0]read_data
);
    reg    [3:0]    ram_reg    [255:0];

integer    i;

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
        for(i=0;i<256;i=i+1)
            ram_reg[i]<= 0;
    end
    else    if(write_en)begin 
        ram_reg[write_addr]<=write_data; 
    end
    else    begin 
        ram_reg[write_addr]<=ram_reg[write_addr]; 
    end
    
end

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
       read_data <=0; 
    end
    else    if(read_en)begin 
        read_data <= ram_reg[read_addr];
    end
    else    begin 
        read_data <= read_data; 
    end
end


endmodule