题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
    reg    [6:0]    cyc_cnt;
    reg             div_flag;
    reg    [3:0]    clk_cnt;
    reg             clk_out_reg;
    
always@(posedge clk_in or negedge rst)begin 
    if(!rst)begin 
       cyc_cnt <= 7'd0; 
    end
    else    if(cyc_cnt == M_N - 1'b1)begin 
       cyc_cnt <= 7'd0; 
    end
    else    begin 
       cyc_cnt <= cyc_cnt + 1'b1; 
    end
end

always@(posedge clk_in or negedge rst)begin
    if(!rst)begin 
        div_flag <= 1'b0;
    end
    else    if((cyc_cnt == (c89 - 1'b1)) || (cyc_cnt == (M_N - 1'b1)))begin 
       div_flag <= ~div_flag; 
    end
    else    begin 
       div_flag <= div_flag; 
    end
end

always@(posedge clk_in or negedge rst)begin 
    if(!rst)begin 
        clk_cnt <= 4'd0;
    end
    else    case(div_flag)
        1'b0 : if(clk_cnt == (div_e - 1'b1))begin 
                    clk_cnt <= 4'd0;              
                end
                else    begin 
                    clk_cnt <= clk_cnt + 1'b1; 
                end
        1'b1 : if(clk_cnt == (div_o - 1'b1))begin 
                    clk_cnt <= 4'd0;
                end
                else    begin 
                    clk_cnt <= clk_cnt + 1'b1; 
                end  
    endcase
end

always@(posedge clk_in or negedge rst)begin 
    if(!rst)begin 
       clk_out_reg <= 1'b0; 
    end
    else    if(((div_flag == 1'b0) && (clk_cnt <= ((div_e>>2)+1))) || ((div_flag) && (clk_cnt <= ((div_o>>2)+1))))begin 
        clk_out_reg <= 1'b1;
    end
    else    
        clk_out_reg <= 1'b0;
end

assign clk_out = clk_out_reg;
//*************code***********//
endmodule