题解 | #状态机-重叠序列检测#
状态机-重叠序列检测
http://www.nowcoder.com/practice/10be91c03f5a412cb26f67dbd24020a9
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
localparam idle = 4'b0000;
localparam s0 = 4'b0001;
localparam s1 = 4'b0010;
localparam s2 = 4'b0100;
localparam s3 = 4'b1000;
reg [3:0] cs,ns;
reg flag1;
always @(posedge clk or negedge rst) begin
if(!rst) cs <= 4'b0;
else cs <= ns;
end
always @(*) begin
case (cs)
idle: ns = data? s0:idle;
s0: ns = data? s0:s1;
s1: ns = data? s2:idle;
s2: ns = data? s3:s1;
s3: ns = data? s0:s1;
default: ns = idle;
endcase
end
always @(posedge clk or negedge rst) begin
if(!rst) flag <= 'b0;
else if(cs==s3) flag<=1'b1;
else flag <= 0;
end
//*************code***********//
endmodule
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
//localparam idle = 3'b000;
//localparam s0 = 3'b001;
//localparam s1 = 3'b010;
//localparam s2 = 3'b100;
//
//reg [2:0] cs,ns;
//reg flag1;
//always @(posedge clk or negedge rst) begin
// if(!rst) cs <= 3'b0;
// else cs <= ns;
//end
//
//always @(*) begin
// case (cs)
// idle: ns = data? s0:idle;
// s0: ns = data? s0:s1;
// s1: ns = data? s2:idle;
// s2: ns = data? s0:s1;
// default: ns = idle;
// endcase
//end
//
//always @(posedge clk or negedge rst) begin
// if(!rst) flag1 <= 'b0;
// else if((cs==s2)&&(data==1)) flag1<=1'b1;
// else flag1 <= 0;
//end
//就离谱，硬是要多一个周期，要么打一拍要么多加个状态，就不能直接flag1就是输出吗
//always @(posedge clk or negedge rst) begin
// if(!rst) flag <= 'b0;
// else flag <= flag1;
//end
localparam s0 = 4'b0001;
localparam s1 = 4'b0010;
localparam s2 = 4'b0100;
localparam s3 = 4'b1000;
reg [3:0] cs,ns;
reg flag1;
always @(posedge clk or negedge rst) begin
if(!rst) cs <= 4'b0;
else cs <= ns;
end
always @(*) begin
case (cs)
idle: ns = data? s0:idle;
s0: ns = data? s0:s1;
s1: ns = data? s2:idle;
s2: ns = data? s3:s1;
s3: ns = data? s0:s1;
default: ns = idle;
endcase
end
always @(posedge clk or negedge rst) begin
if(!rst) flag <= 'b0;
else if(cs==s3) flag<=1'b1;
else flag <= 0;
end
//*************code***********//
endmodule
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