题解 | #不重叠序列检测#
不重叠序列检测
http://www.nowcoder.com/practice/9f91a38c74164f8dbdc5f953edcc49cc
感觉这题clk采样怪怪的，用的是移位寄存器方法，在modelsim下仿真，此代码为正确的(但在牛客的iverilog中仿真，就错误了)。为了实现时序的移位寄存器和cnt同时判断match，对cnt打了一拍。本菜鸟被困扰了一下午，欢迎指正交流
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
reg [5:0] seq;
reg [3:0] counter;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seq <= 6'b0;
match <= 1'b0;
not_match <= 1'b0;
end
else
seq <= { seq[4:0], data };
end
always@(posedge clk) begin
if(!rst_n) begin
counter <= 0;
end
else if(counter=='d5)
counter <= 0;
else begin
counter <= counter + 1;
end
end
reg flag;
always@(posedge clk) begin
if(!rst_n) begin
flag <= 0;
end
else if(counter=='d5)
flag <= 1;
else begin
flag <= 0;
end
end
always@(posedge clk)begin
if( {seq[4:0],data}==6'b011100 && flag ) begin
match <= 1;
end
else begin
match <= 0;
end
end
always@(posedge clk)begin
if( {seq[4:0],data}!=6'b011100 && flag ) begin
not_match <= 1;
end
else begin
not_match <= 0;
end
end
endmodule
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