题解 | #移位运算与乘法#

包含测试代码文件及波形

////*************code***********//
//endmodule
`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
    
    reg [1:0] cnt;
    reg [7:0]reg_d;
    
    
    always@(posedge clk or negedge rst)begin
        if(!rst)begin
            cnt <= 2'b00;
        end
        else
            cnt <= cnt + 1;
    end
    always@(posedge clk or negedge rst)begin
        if(!rst)begin
            reg_d <= 8'd0;
            input_grant <= 1'b0;
        end
        else if(cnt == 2'd0)begin
            reg_d <=d;
            input_grant <= 1'b1;
        end
        else begin
            reg_d <= reg_d;
            input_grant <= 1'b0;
        end
    end
             
                
    always@(*)begin
        case(cnt)
            2'b01:begin
                out =  reg_d;
            end
            2'b10:begin
                out = (reg_d<<2)-reg_d;
            end
            2'b11:begin
                out = (reg_d<<3)-reg_d;
            end
            2'b00:begin
                out <= (reg_d<<3);
            end
        endcase
        end
    
            


//*************code***********//
endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/09 15:50:44
// Design Name: 
// Module Name: ddd_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ddd_tb();
    reg clk,rst;
    reg[7:0] d;
    wire input_grant;
    wire [10:0]out;
    
    initial begin clk = 0;end
    
    always #50 clk = ~clk;
    
    initial begin
    d = 0;
    rst = 0;
    
    #200 rst = 1;
    d=  8'd8;
    #300 d = 8'd10;
    
    # 300 d = 8'd20;
    end
    
    multi_sel inst(.clk(clk),
                   .rst(rst),
                   .d(d),
                   .out(out),
                   .input_grant(input_grant)
                   );
    
    
    

endmodule

注意第二段为组合逻辑，因此case块那不要弄错了