`timescale 1ns/1ns module data_driver( input clk_a, input rst_n, input data_ack, output reg [3:0]data, output reg data_req ); reg[0:0]data_ack_r; reg[0:0]data_ack_rr; reg[0:0]data_ack_rrr; always@(posedge clk_a or negedge rst_n)begin if(!rst_n)begin data_ack_r <= 0; data_ack_rr <= 0; data_ack_...
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