题解 | 脉冲同步器（快到慢）

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);

reg		sig_a_r1;
reg		sig_a_r2;
reg		sig_a_r3;
wire    sig_a_r ;

always@(posedge clka or negedge rst_n)
begin
	if(!rst_n)
	begin
		sig_a_r1	<=	1'b0;
		sig_a_r2	<=	1'b0;
		sig_a_r3	<=	1'b0;
	end 
	else
	begin
		sig_a_r1	<=	sig_a;
		sig_a_r2	<=	sig_a_r1;
		sig_a_r3	<=	sig_a_r2;
	end
end

assign 	sig_a_r = sig_a_r3 | sig_a_r2 | sig_a_r1;

reg   sig_b_r1;
reg   sig_b_r2;

always@(posedge clkb or negedge rst_n)
begin
	if(!rst_n)
	begin
		sig_b_r1	<=	1'b0;
		sig_b_r2	<=	1'b0;
	end
	else
	begin
		sig_b_r1	<=	sig_a_r ;
		sig_b_r2	<=	sig_b_r1;
	end
end

assign  sig_b = sig_b_r2;

    
endmodule