题解 | 多bit MUX同步器

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
//涉及到两个信号（data_in、data_en）的跨时钟域传输（打两拍）
//data_in 寄存器寄存
reg [3:0] data_reg,data_reg1,data_reg2;
reg data_en_a,data_en_b1, data_en_b2;
always@(posedge clk_a or negedge arstn)
if(!arstn)  begin
  data_en_a  <= 0;
  data_reg <= 0;
end
else begin
  data_reg <= data_in;
  data_en_a  <= data_en;
end


always@(posedge clk_b or negedge brstn)
if(!brstn) begin
  data_reg1 <= 0;
  data_reg2 <= 0;
  data_en_b1 <= 0;
  data_en_b2 <= 0;
end
else begin
  data_reg1 <= data_reg;
  data_reg2 <= data_reg1;
  data_en_b1 <= data_en_a;
  data_en_b2 <= data_en_b1;
end

//data_en
always@(posedge clk_b or negedge brstn)
if(!brstn)
  dataout <= 0;
else
  dataout <= data_en_b2 ? data_reg2 : dataout;
endmodule