题解 | 根据RTL图编写Verilog程序
根据RTL图编写Verilog程序
https://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg data_in_reg; always@(posedge clk or negedge rst_n) if(!rst_n)begin data_in_reg <= 0; data_out <= 0; end else begin data_in_reg <= data_in; data_out <= data_in&&!data_in_reg; end endmodule
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