题解 | 交通灯

交通灯

https://www.nowcoder.com/practice/b5ae79ff08804b61ad61f749eaf157ba

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
//用状态机处理：
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  current_state <= 3'd0;
else
  current_state <= next_state;

reg [7:0] clock1;

always@(*)//下个状态跳转用组合逻辑
 case(current_state)
 3'd0:next_state <= (clock1==8'd8)? 3'd1 :3'd0;
 3'd1:next_state <= (clock1==8'd1)? 3'd2 :3'd1;
 3'd2:next_state <= (clock1==8'd1)? 3'd3 :3'd2;
 3'd3:next_state <= (clock1==8'd1)? 3'd1 :3'd3;
 default:next_state <= 3'd0;
 endcase

always@(posedge clk or negedge rst_n)
if(!rst_n)
  clock1 <= 8'd10;
else begin
 case(current_state)
 3'd0: clock1 <= (clock1==8'd8)? 8'd10 :(clock1 - 1'b1);//红灯
 3'd1: clock1 <= (clock1==8'd1)? 8'd5  :(clock1 - 1'b1);//黄灯
 3'd2: clock1 <= (clock1==8'd1)? 8'd60 :(clock1 - 1'b1);
 3'd3: clock1 <= ((clock1==8'd1)||(pass_request &&(clock1 > 8'd10))) ? 8'd10 : (clock1 -1'b1);
 default:clock1 <= 8'd10;
 endcase
end

always@(posedge clk or negedge rst_n)
if(!rst_n) begin
    red <= 0;
    yellow <= 0;
    green <= 0;
end
else begin
    red <= (next_state==3'd1) ? 1 : 0;
    yellow <= (next_state ==3'd2)? 1 : 0;
    green <= (next_state==3'd3) ? 1 : 0;
end


assign clock = clock1;
endmodule

这个题真的是，好多东西都不说。他的要求是要：异步复位之后从10开始计数到8然后：红灯-黄灯-绿灯-红灯；

说一个我在这里面碰到的问题：就是我开始是用的类似于下面的代码，然后状态一直在几个状态之间异常跳转。

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
//用状态机处理：
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  current_state <= 3'd0;
else
  current_state <= next_state;

reg [7:0] clock1;


always@(posedge clk or negedge rst_n)
if(!rst_n) begin
    clock1 <= 8'd10;
    next_state <= 3'd0;
end
else begin
 case(current_state)
 3'd0:begin
      next_state <= 3'd1;//黄灯
      clock1 <= (clock1==8'd8)? 8'd10 :(clock1 - 1'b1);//红灯
    end
 3'd1: begin
        next_state <= (clock1==8'd1)? 3'd2 :3'd1;
        clock1 <= (clock1==8'd1)? 8'd5  :(clock1 - 1'b1);//黄灯
 end
 3'd2: begin
       next_state <= (clock1==8'd1)? 3'd3 :3'd2;
       clock1 <= (clock1==8'd1)? 8'd60 :(clock1 - 1'b1);
 end
 3'd3: begin
       next_state <= (clock1==8'd1)? 3'd1 :3'd3;
	   clock1 <= ((clock1==8'd1)||(pass_request &&(clock1 > 8'd10))) ? 8'd10 : (clock1 -1'b1);
end
 default:begin 
         next_state <= 3'd0;
         clock1 <= 8'd10;
    end
 endcase
end

always@(posedge clk or negedge rst_n)
if(!rst_n) begin
    red <= 0;
    yellow <= 0;
    green <= 0;
end
else begin
    red <= (next_state==3'd1) ? 1 : 0;
    yellow <= (next_state ==3'd2)? 1 : 0;
    green <= (next_state==3'd3) ? 1 : 0;
end


assign clock = clock1;
endmodule