题解 | 自动售卖机

`timescale 1ns/1ns

module sale(
   input                clk   ,
   input                rst_n ,
   input                sel   ,//sel=0,5$dranks,sel=1,10&=$drinks
   input          [1:0] din   ,//din=1,input 5$,din=2,input 10$
 
   output   reg  [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinks
   output	reg        change_out   
);

parameter IDLE = 4'd0;
parameter S1 = 4'd1;
parameter S10 = 4'd2;
parameter S11 = 4'd3;
parameter S12 = 4'd4;
parameter S2 = 4'd5;
parameter S20 = 4'd6;
parameter S21 = 4'd7;
parameter S22 = 4'd8;
parameter S23 = 4'd9;

reg [3:0] cstate;
reg [3:0] nstate;

always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cstate <= 0;
    else
        cstate <= nstate;
end

always@(*) begin
    case(cstate)
        IDLE:begin
            if(sel == 0)
                nstate = S1;
            else
                nstate = S2;
        end
        S1:begin
            if(din == 0)
                nstate = S10;
            else if(din == 1)
                nstate = S11;
            else if(din == 2)
                nstate = S12;
            else
                nstate = S1;
        end
        S10:begin
            if(din == 0)
                nstate = S10;
            else if(din == 1)
                nstate = S11;
            else if(din == 2)
                nstate = S12;
            else
                nstate = S10;
        end
        S11:begin
            if(sel)
                nstate = S2;
            else if(din == 0)
                nstate = S10;
            else if(din == 1)
                nstate = S11;
            else if(din == 2)
                nstate = S12;
            else
                nstate = S11;
        end
        S12:begin
            if(sel)
                nstate = S2;
            else if(din == 0)
                nstate = S10;
            else if(din == 1)
                nstate = S11;
            else if(din == 2)
                nstate = S12;
            else    
                nstate = S12;
        end
        S2:begin
            if(din == 0)
                nstate = S20;
            else if(din == 1)
                nstate = S21;
            else if(din == 2)
                nstate = S22;
            else 
                nstate = S2;
        end
        S20:begin
            if(din == 0)
                nstate = S20;
            else if(din == 1)
                nstate = S21;
            else if(din == 2)
                nstate = S22;
            else
                nstate = S20;
        end
        S21:begin
            if(din == 0)
                nstate = S21;
            else if(din == 1)
                nstate = S22;
            else if(din == 2)
                nstate = S23;
            else
                nstate = S21;
        end
        S22:begin
            if(!sel) 
                nstate = S1;
            else if(din == 0)
                nstate = S20;
            else if(din == 1)
                nstate = S21;
            else if(din == 2)
                nstate = S22;
            else
                nstate = S22;
        end
        S23:begin
            if(!sel)
                nstate = S1;
            else if(din == 0)
                nstate = S20;
            else if(din == 1)
                nstate = S21;
            else if(din == 2)
                nstate = S22;
            else
                nstate = S23;
        end
        default:begin
            nstate = IDLE;
        end
    endcase
end

always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        drinks_out <= 2'b0;
        change_out <= 0;
    end
    else if(nstate == S11) begin
        drinks_out <= 1;
        change_out <= 0;
    end
    else if(nstate == S12) begin
        drinks_out <= 1;
        change_out <= 1;
    end
    else if(nstate == S22) begin
        drinks_out <= 2;
        change_out <= 0;
    end
    else if(nstate == S23) begin
        drinks_out <= 2;
        change_out <= 1;
    end
    else begin
        drinks_out <= 0;
        change_out <= 0;
    end
end


endmodule