题解 | 状态机-重叠序列检测

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//重叠检测
//method1:移位寄存
// reg [3:0] data_reg;
// always@(posedge clk or negedge rst)
//   if(!rst)
//     data_reg <= 0;
//   else
//     data_reg <= {data_reg[2:0],data};//比data_in慢了一拍

// always@(posedge clk or negedge rst)
// if(!rst)
//   flag <= 0;
// else if(data_reg == 4'b1011)
//   flag <= 1;//刚好延迟一拍
// else
//   flag <= 0;
//*************code***********//
//（1）Moore型状态机：输出信号只取决于当前状态。(比mealy型多一拍)
//（2）Mealy型状态机：输出信号不仅取决于当前状态，还取决于输入信号的值

//寄存器输出，在序列检测完成下一拍输出检测有效-->moore型
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst)
if(!rst)
  current_state <= 0;
else
  current_state <= next_state;

always@(*)
  case(current_state)
    3'd0:next_state = data ? 3'd1:3'd0;
    3'd1:next_state = (data==0) ? 3'd2:3'd1;
    3'd2:next_state = data ? 3'd3:3'd1;
    3'd3:next_state = data ? 3'd4:3'd1;
    3'd4:next_state = data ? 3'd1:3'd2;
    default:next_state <= 3'd0;
  endcase

always@(posedge clk or negedge rst)
  if(!rst)
   flag <= 0;
else if(current_state==3'd4)
  flag <= 1;
else
  flag <= 0;
endmodule