题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg [3:0] data_reg;

always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	data_reg <= 'b0;
end
else if(data_valid)begin
	data_reg <= {data_reg[2:0],data};
end
else begin
	data_reg <= data_reg;
end
end



always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	match <= 1'b0;
end
else if((data_reg[2:0] == 3'b011)&&(data==1'b0)&&(data_valid==1'b1))begin
	//这里注意时序，因为data_reg相对data_valid慢一拍，所以判断条件要同时满足data_valid == 1b'1 和data_reg[2:0] == 3'b011，同时data==1'b0，但还没更新到data_reg，所以条件不能是data_reg[3:0]==4'b0110
	match <= 1'b1;
end
else begin
	match <= 1'b0;
end
end








endmodule