题解 | 优先编码器电路①

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

always@(*)begin
    casex({I_n[0],I_n[1],I_n[2],I_n[3],I_n[4],I_n[5],I_n[6],I_n[7],I_n[8]})
        9'b1111_1111_1: Y_n <= 4'b1111;
        9'bxxxx_xxxx_0: Y_n <= 4'b0110;
        9'bxxxx_xxx0_1: Y_n <= 4'b0111;
        9'bxxxx_xx01_1: Y_n <= 4'b1000;
        9'bxxxx_x011_1: Y_n <= 4'b1001;
        9'bxxxx_0111_1: Y_n <= 4'b1010;
        9'bxxx0_1111_1: Y_n <= 4'b1011;
        9'bxx01_1111_1: Y_n <= 4'b1100;
        9'bx011_1111_1: Y_n <= 4'b1101;
        9'b0111_1111_1: Y_n <= 4'b1110;
        
    endcase
end
endmodule