题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
//虽然这道题很简单，但题目要求状态机，那还是三段式吧
reg [1:0] crt_state,nxt_state;
always@(posedge clk or negedge rst) begin
 if(!rst)
   crt_state <= 2'd0;
  else
   crt_state <= nxt_state;
end

always@(*) begin
 case(crt_state)
  2'd0: nxt_state <= 2'd1;
  2'd1: nxt_state <= 2'd2;
  2'd2: nxt_state <= 2'd3;
  2'd3: nxt_state <= 2'd0;
  default: nxt_state <= 2'd0;
 endcase
end

always@(posedge clk or negedge rst) begin
 if(!rst)
   clk_out <= 0;
  else if(nxt_state==2'd1)
   clk_out <= 1;
  else
   clk_out <= 0;
end
//*************code***********//
endmodule