题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg [4:0]cnt_p;
reg [6:0]cnt;
reg clk;
assign clk_out=clk;


always@(posedge clk_in or negedge rst)
if(!rst)begin
    clk<=0;
    cnt_p<=0;
    cnt<=0;
end else begin
    if(cnt==M_N)begin
    cnt<=1;
    clk<=1;
    end else if(cnt<M_N)cnt<=cnt+1'b1;
end

always@(posedge clk_in or negedge rst)
if(!rst)begin
    clk<=0;
    cnt_p<=0;
    cnt<=0;
end else begin
    if(cnt<c89)begin
        if(cnt_p==(div_e>>1))begin
            cnt_p<=cnt_p+1'b1;
            clk<=0;  
        end else if(cnt_p==(div_e))begin
            cnt_p<=1'b1;
            clk<=1;  
        end else if(cnt_p<(div_e>>1))begin
            cnt_p<=cnt_p+1'b1;
            clk<=1;
        end else if(cnt_p>(div_e>>1)&(cnt_p<div_e))begin
            cnt_p<=cnt_p+1'b1;
            clk<=0;
        end
    end if(cnt==c89)begin
            cnt_p<=1'b1;
            clk<=1; 
    end else if(cnt>c89)begin
        if(cnt_p==((div_o-1'b1)>>1))begin
            cnt_p<=cnt_p+1'b1;
            clk<=0;  
        end else if(cnt_p==(div_o))begin
            cnt_p<=1'b1;
            clk<=1;  
        end else if(cnt_p<((div_o-1'b1)>>1))begin
            cnt_p<=cnt_p+1'b1;
            clk<=1;
        end else if(cnt_p>((div_o-1'b1)>>1)&(cnt_p<div_o))begin
            cnt_p<=cnt_p+1'b1;
            clk<=0;
        end
    end
   

end

//*************code***********//
endmodule