题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output  [3:0]data
);

reg [3:0]		rom[7:0]		;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		rom[0]			<=		'd0		;
		rom[1]			<=		'd2		;
		rom[2]			<=		'd4		;
		rom[3]			<=		'd6		;
		rom[4]			<=		'd8		;
		rom[5]			<=		'd10	;
		rom[6]			<=		'd12	;
		rom[7]			<=		'd14	;
	end
end

assign	data = rom[addr];


endmodule