题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns



module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

    parameter S0 = 'd0, S1 = 'd1, S2 = 'd2, S3 = 'd3 ;
    reg [2:0]	current_state;
    reg [2:0]	next_state;
	
    always@(posedge clk or negedge rst)
    begin
        if(rst == 1'b0)begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end   
    
    always@(*)begin
        case(current_state)
            S0:begin
                next_state = data ? S1 : S0;
            end
            S1:begin
                next_state = data ? S2 : S1;
            end
            S2:begin
                next_state = data ? S3 : S2;
            end
            S3:begin
                next_state = data ? S0 : S3;
            end
            default:begin  next_state = S0; end
        endcase
    end
    
    always@(posedge clk or negedge rst)begin
        if(rst == 1'b0)begin
            flag <= 1'b0;
        end
        else begin
            if(current_state == S3)begin
				if (data) flag <= 1'b1;
				else flag <= 1'b0;
            end
            else begin
                flag <= 1'b0;
            end
        end
    end
 
endmodule