题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0] cnt;
reg [120-1:0] tmp;
always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)begin
		cnt <= 0;
	end else begin
		if(valid_in) cnt <= cnt == 'd15 ? 'd0 : cnt + 1;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)begin
		tmp <= 0;
	end else begin
		if(valid_in) tmp <= {tmp[95:0], data_in};
	end
end

always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)begin
		data_out <= 0;
		valid_out <= 0;
	end else begin
		valid_out <= 0;
		if(valid_in)begin
			if(cnt == 'd5)begin
				data_out <= {tmp[119:0], data_in[23:16]};
				valid_out <= 1;
			end else if(cnt == 'd10) begin
				data_out <= {tmp[111:0], data_in[23:8]};
				valid_out <= 1;
			end else if(cnt == 'd15) begin
				data_out <= {tmp[103:0], data_in[23:0]};
				valid_out <= 1;
			end
		end
	end
end

endmodule