题解 | #序列发生器#

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);


parameter IDLE = 6'b000001,
            S1= 6'b000010,
            S2=6'b000100,
            S3 = 6'b001000,
            S4 =6'b010000,
            S5 = 6'b100000;

reg [5:0] curr_state, next_state;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            curr_state <=IDLE;
        end
        else begin
            curr_state <= next_state;
        end
    end

    always @(*) begin
        case (curr_state)
            IDLE: next_state <= S1;
            S1:next_state <=S2;
            S2:next_state <= S3;
            S3:next_state <=S4;
            S4:next_state<= S5;
            S5:next_state <=IDLE;
            default: next_state <= IDLE;
        endcase
    end

    always @(posedge clk or negedge rst_n) begin
		if(!rst_n)
		data <= 0;
		else
        if (curr_state == S2 || curr_state == S4 || curr_state == S5) begin
            data <= 1;
        end
        else
        data <= 0;
    end
endmodule