题解 | #编写乘法器求解算法表达式#

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);

wire [8:0] a12;
wire [8:0] b5;

assign a12=(a<<3)+(a<<2);
assign b5=(b<<2)+b;

reg [8:0] c_reg,c_reg_d1;

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		c_reg<=0;
	else
		c_reg<=a12+b5;
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		c_reg_d1<=0;
	else
		c_reg_d1<=c_reg;
end

assign c=c_reg_d1;


endmodule