题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] count;
reg [5:0] data_r;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        count <= 0;
        data_r <= 0;
    end
    else if(valid_a)begin
        if(count == 3'd5)begin
            count <= 3'd0;
            data_r[count] <= data_a;
        end
        else begin
            count <= count + 1'b1;
            data_r[count] <= data_a; 
        end
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        ready_a <= 0;
        valid_b <= 0;
        data_b <= 0;
    end
    else if(count == 5'd5)begin
        data_b <= data_r;
        valid_b <= 1;
    end
    else begin
        ready_a <= 1;
        valid_b <= 0;
    end
end

endmodule