题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output reg valid_in ,
	output reg dout
	);

//*************code***********//
reg [1:0] flow;
reg [3:0] d_r;

//*************code***********//

always@(posedge clk or negedge rst)
begin
	if(!rst)
		flow<=2'd0;
	else if(flow==2'd3)
		flow<=2'd0;
	else	
		flow<=flow+1;
end

always @(posedge clk or negedge rst)
begin
	if(!rst)
		valid_in <= 1'b0;
	else if(flow==2'd3)
		valid_in <= 1'b1;
	else
		valid_in <=1'b0;
end

always@(posedge clk or negedge rst)
begin
	if(!rst)
		d_r<=4'd0;
	else if(flow==2'd3)
		d_r<=d;
	else
		d_r <= {d_r,1'b0};
end

always @(posedge clk or negedge rst)
begin
	if(!rst)
		dout<=1'b0;
	else if(flow==2'd3)
		dout <= d[3];
	else
		dout <= d_r[2];
end
endmodule