题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				  clk 		,   
	input 			      rst_n		,
	input				  valid_in	,
	input	[7:0]		  data_in	,
 
 	output  reg			  valid_out,
	output  reg [11:0]    data_out
);

	// 8*3 = 12*2
	// cnt = 0,1, not vail
	// cnt = 2,3, vail

	reg [7:0] data_lock;
	reg [1:0] cnt;

	always @ (posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			cnt <= 2'd0;
		end
		else begin
			if (cnt==2'd3) begin
				cnt <= valid_in ? 2'd1 : 2'd0;
			end
			else begin
				cnt <= valid_in ? (cnt + 2'd1) : cnt;
			end
		end
	end

	always @ (posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			data_lock <= 'b0;
			data_out  <= 'b0;
		end
		else begin
			if (valid_in) begin
				data_lock <= data_in;
				if (cnt==2'd1) 
					data_out <= {data_lock, data_in[7:4]};
				else if (cnt==2'd2)
					data_out <= {data_lock[3:0], data_in};
				else 
					// data_out <= 'b0;
					data_out <= data_out;
			end
			else begin
				data_lock <= data_lock ;
				data_out  <= data_out  ;
			end
		end
	end

	always @ (posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			valid_out <= 1'b0;
		end
		else begin
			if (valid_in && 
				((cnt==2'd1) || (cnt==2'd2))
			)
				valid_out <= 1'b1;
			else 
				valid_out <= 1'b0;
		end
	end
endmodule

`timescale 1ns/1ns

module testbench();
    reg clk, rst_n;
    reg valid_in;
    reg [7:0] data_in;
    wire valid_out;
    wire [11:0] data_out;

    initial begin
        clk = 0;
        rst_n = 1;
        #10
        rst_n = 0;
        #30 
        rst_n = 1;
        
        repeat(20) begin
            @(negedge clk);
            // randomize set valid_in high
            valid_in = $random;
            data_in = $random;
        end
    end

    always begin
        #10 clk=~clk;
    end

    width_8to12 dut(.*);

    initial begin
      #1000 $finish;
    end

    initial begin
		$dumpfile("out.vcd");
		$dumpvars(0, testbench);
	end
endmodule