题解 | #序列发生器#
序列发生器
https://www.nowcoder.com/practice/1fe78a981bd640edb35b91d467341061
`timescale 1ns/1ns
module sequence_generator(
input clk,
input rst_n,
output reg data
);
reg [5:0] ref;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
ref <= 6'b001011;
else
ref <= {ref[4:0],ref[5]};
always @ (posedge clk or negedge rst_n)
if (!rst_n)
data <= 0;
else
data <= ref[5];
endmodule
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