题解 | #状态机-重叠序列检测#
状态机-重叠序列检测
https://www.nowcoder.com/practice/10be91c03f5a412cb26f67dbd24020a9
`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// wire rst_n; assign rst_n = rst; reg [3:0] data_reg; always @(posedge clk or negedge rst_n) begin if(~rst_n) data_reg <= 4'b0; else data_reg <= {data_reg[2:0], data}; end always @(posedge clk or negedge rst_n) begin if(~rst_n) flag <= 1'b0; else flag <= (data_reg==4'b1011); end //*************code***********// endmodule