题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
reg [3:0] mem [0:7];
integer i;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		for(i=0;i<8;i=i+1)begin
			mem[i]<=0;
		end
	end
	else begin
		if(write_en)begin
			mem[write_addr]<=write_data;
		end
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)read_data<=0;
	else begin
		if(read_en)read_data<=mem[read_addr];
		else read_data<=0;
	end
end
endmodule