题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
parameter idle=0,s0_half=1,s0_one=2,s0_one_half=3,s0_two=4;
parameter s1_half=5,s1_one=6,s1_one_half=7,s1_two=8,s1_two_half=9,s1_three=10;
reg [3:0]cs,ns;
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		cs<=idle;
	end
	else begin
		cs<=ns;
	end
end
always@(*)begin
	if(!rst) ns=idle;
	else begin
		case(cs)
		idle:ns=sel?(d1?s1_half:d2?s1_one:ns):(d1?s0_half:d2?s0_one:ns);//和上题一样需要锁存ns值，因为激励d1,d2在上升沿和下降沿值都变了
		s0_half:ns=d1?s0_one:d2?s0_one_half:ns;
		s0_one: ns=d1?s0_one_half:d2?s0_two:ns;
		s0_one_half:ns=idle;
		s0_two:ns=idle;
		s1_half:ns=d1?s1_one:d2?s1_one_half:ns;
		s1_one:ns=d1?s1_one_half:d2?s1_two:ns;
		s1_one_half:ns=d1?s1_two:d2?s1_two_half:ns;
		s1_two:ns=d1?s1_two_half:d2?s1_three:ns;
		s1_two_half:ns=idle;
		s1_three:ns=idle;
		default:ns=idle;
		endcase
	end
end
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		out1<=0;
		out2<=0;
		out3<=0;
	end
	else begin
		if(ns==s0_one_half)begin
			out1<=1;
			out2<=0;
			out3<=0;
		end
		else if(ns==s0_two)begin
			out1<=1;
			out2<=0;
			out3<=1;
		end
		else if(ns==s1_two_half)begin
			out1<=0;
			out2<=1;
			out3<=0;
		end
		else if(ns==s1_three)begin
			out1<=0;
			out2<=1;
			out3<=1;
		end
		else begin
			out1<=0;
			out2<=0;
			out3<=0;
		end
	end
end
//*************code***********//
endmodule