题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg [1:0]cnt;
reg [11:0]data_reg;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt<=0;
	end
	else begin
		if(valid_in)begin
			if(cnt<2'd2) cnt<=cnt+1;
			else         cnt<=0;
		end 
		else begin
			cnt<=cnt;
		end
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)		valid_out<=0;
	else if((cnt==2'd1 | cnt==2'd2) &valid_in)valid_out<=1;
	else valid_out<=0;
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) data_reg<=0;
	else begin
		if(valid_in)data_reg<={data_reg[3:0],data_in};
		else  data_reg<=data_reg;
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) data_out<=0;
	else begin
		if(cnt==2'd1 &valid_in) data_out<={data_reg[7:0],data_in[7:4]};
		else if(cnt==2'd2 & valid_in) data_out<={data_reg[3:0],data_in[7:0]};
		else data_out<=data_out;
	end
end

endmodule