题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

	reg [5:0] buffer ;
	reg [2:0] cnt    ;

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
	        buffer <= 6'b001011 ;
        else 
		    buffer <= buffer    ;
	end

	always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
	        cnt <= 'd5          ;
        else if(cnt == 'd0)
		    cnt <= 'd5          ;
	    else 
		    cnt <= cnt - 1'd1   ;
	end

	always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
	        data <= 'd0          ;
        else 
		    data <= buffer[cnt]  ;
	end

endmodule