题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    parameter Idle='d0,S1='d1,S2='d2,S3='d3,S4='d4,S5='d5,S6='d6,Fail='d7;
    reg[$clog2(8)-1:0] state;
    reg[$clog2(8)-1:0] nx_state;
    reg[$clog2(6)-1:0] counter;
    always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin

            state<='d0;
        end
        else begin
            state<=nx_state;
        end
    end
    always@(*)begin
		if(~rst_n)begin
			nx_state='d0;

		end
		else begin
        case(state)
            Idle: nx_state=data?Fail:S1;
            S1: nx_state=data?S2:Fail;
            S2: nx_state=data?S3:Fail;
            S3: nx_state=data?S4:Fail;
            S4: nx_state=data?Fail:S5;
            S5: nx_state=data?Fail:S6;
            S6: nx_state= data?Fail:S1;
            Fail: nx_state= counter=='d6&&data==0?S1:Fail;
			default: nx_state=Idle;
        endcase
		end
    end

    always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
        match<='d0;
        not_match<='d0;
       // counter<='d0;
        end 
        else begin
            match     <= nx_state==S6;
            not_match <= counter==5&&nx_state==Fail;
            


        end
    end
	always@(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
			counter<='d0;
        end 
        else begin
			counter<=counter=='d6?'d1:counter+1'b1;
		end
	end
   
endmodule