题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output [1:0]mux_out
);
//*************code***********//
reg [1:0] mux_out_my;
always@(*)
begin
    case(sel)
    2'd0:  mux_out_my = d3;
    2'd1:  mux_out_my = d2;
    2'd2:  mux_out_my = d1;
    2'd3:  mux_out_my = d0;
    default:  mux_out_my = 2'd0;
    endcase
end

assign mux_out = mux_out_my;
//*************code***********//
endmodule