题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//

reg [6:0] cnt_87;
reg [2:0] cnt_8;
reg [3:0] cnt_9;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt_87 <= 0;
    end
    else if(cnt_87 == M_N - 1) begin
        cnt_87 <= 0;
    end
    else begin
        cnt_87 <= cnt_87 + 1'b1;
    end
end

always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt_8 <= 0;
    end
    else if((cnt_87 <= c89-1)) begin
        if(cnt_8 == div_e - 1 ) begin
            cnt_8 <= 0;
        end
        else begin
            cnt_8 <= cnt_8 + 1'b1;
        end
    end
end

always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt_9 <= 0;
    end
    else if((cnt_87 > c89-1)) begin
        if(cnt_9 == (div_o - 1)) begin
            cnt_9 <= 0;
        end
        else begin
            cnt_9 <= cnt_9 + 1'b1;
        end
    end
end

reg clk_out_reg;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_out_reg <= 0;
    end
    else if(cnt_87 <= c89 - 1) begin //3个8分频,8分频翻转
        clk_out_reg <= (cnt_8 == 0 || cnt_8 == div_e/2) ? (~clk_out_reg) : clk_out_reg ;
    end
    else if(cnt_87 > c89 - 1) begin//7个9分频,9分频翻转
        clk_out_reg <= (cnt_9 == 0 || (cnt_9 == (div_o-1)/2)) ? (~clk_out_reg) : clk_out_reg ;
    end
end

assign clk_out = clk_out_reg;


//*************code***********//
endmodule