题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
parameter S5 = 3'd5;


reg [2:0] c_state;
reg [2:0] n_state;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= S0;
	end
	else begin
		c_state <= n_state;
	end
end

reg once;
always @(*) begin
	if(!rst) begin
		n_state <= S0;
	end
	else begin
		case(c_state)
			S0:
				//n_state <= (data == 1)?S1:S0;
				case(data)
					0: begin once <= 0; n_state <= S0;end
					1: begin once <= 0; n_state <= S1;end
				endcase
			S1:
				//n_state <= (data == 0)?S2:S0;
				case(data)
					0: n_state <= S2;
					1: n_state <= S0;
				endcase
			S2:
				//n_state <= (data == 1)?S3:S0;
				case(data)
					0: n_state <= S0;
					1: n_state <= S3;
				endcase
			S3:
				//n_state <= (data == 1)?S4:S2;
				case(data)
					0: n_state <= S2;
					1: n_state <= S4;
				endcase
			S4:
				//n_state <= (data == 1)?S5:S2;
				case(data)
					0: n_state <= S2;
					1: n_state <= S5;
				endcase
			S5: 
				//n_state <= (data == 1)?S1:S0;
				begin n_state <= S0; once <= 1; end
			default: n_state <= S0;
		endcase
	end
end

always @(*) begin
	if(!rst) begin
		flag <= 0;
	end
	else if(c_state == S5 && once == 1) begin
		flag <= 1;
	end
	else begin
		flag <= 0;
	end
end




//*************code***********//
endmodule