题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg tmp;
always@(posedge clk or negedge rst)
begin
    if(!rst) 
        begin
            tmp<=1'b0;
        end
    else
    begin
        tmp<=tmp^data;
    end
end
always@(posedge clk or negedge rst)
begin
    if(!rst) 
        begin
            q<=1'b0;
        end
    else
    begin
        q<=q^tmp;
    end
end


//*************code***********//
endmodule