题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
	reg [3:0] seq;
 	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			seq <= 0;
		end	
		else begin
			if(data_valid) begin
				seq <= {seq[2:0],data};
			end
			else begin
				seq <= 4'b0;
			end
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			match <= 0;
		end	
		else begin
			if(data_valid && {seq[2:0],data} == 4'b0110) begin
				match <= 1;
			end
			else begin
				match <= 0;
			end
		end
	end
  
endmodule //牛牛的答案提前一个时钟周期