题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);
	
	reg [1:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 0;
		end
		else if(valid_a && ready_a) begin
				cnt <= cnt + 1'b1;
		end
		else begin
			cnt <= cnt;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <= 0;
		end
		else if(valid_a && ready_a) begin
			if(cnt==2'b0) begin
			data_out <= data_in;
			end
			else begin
			data_out <= data_out + data_in;
			end
		end
		else begin
			data_out <= data_out;
		end
	end

	assign ready_a = ready_b | ~valid_b;

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			valid_b <= 0;
		end
		else if(valid_a && (cnt == 2'd3) && ready_a) begin
			valid_b <= 1;
		end
		else if(valid_b && ready_b) begin
			valid_b <= 0;
		end
	end

endmodule