题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);

	reg [4:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 0;
		end
		else if(cnt >= 19) begin
			cnt <= 0;
		end
		else begin
			cnt <= cnt + 1'b1;
		end
	end

	reg flag;
	// 三角波模式下，标志位控制
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            flag <= 0;
        else
            flag <= wave_choise!=2 ? 0:
                    wave       ==1 ? 1:
                    wave       ==19? 0:
                    flag;
    end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			wave <= 0;
		end
		else begin
			case(wave_choise)
				0:	wave <= (cnt == 9)?(20):(cnt == 19?0:wave);
				//0:	wave <= (cnt >= 9)?(20):(0);
				1:	wave <= (wave == 20)?0:(wave + 1'b1);
				2:  wave <= (flag == 0)?(wave - 1'b1):(wave + 1'b1);
				default: wave <= 0;
			endcase
		end
	end


endmodule