题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output reg [1:0]mux_out
);
//*************code***********//
reg [1:0] mux_out1;
always @(*) begin
    case(sel) 
        0: mux_out=d3;
        1: mux_out=d2;
        2: mux_out=d1;
        3: mux_out=d0;
        default: mux_out=2'b00;
    
    endcase
end
//assign mux_out=mux_out1;
//*************code***********//
//assign mux_out = sel[0]?(sel[1]?d0:d2):(sel[1]?d1:d3);
endmodule