题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,

	output reg match
);

reg [8:0]data;


always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data <= 9'b0;
	else 
	    data <= (data << 1) + a;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    match <= 1'b0;
	else if (data[8] == 1'b0 && data[7] == 1'b1 && data[6] == 1'b1 && data[2] == 1'b1 && data[1] == 1'b1 && data[0] == 1'b0)
	    match <= 1'b1;
	else
	    match <= 1'b0;




endmodule