题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,

	output wire data_out
);

wire q1;
wire q2;

DFF data_in_reg
(
    .clk(clk),
	.SCLR(1'b0),
	.CLRN(rst_n),
	.D(data_in),

	.Q(q1)
);

and1 always1
(
    .data1(data_in),
	.data2(~q1),

	.out(q2)
);

DFF data_out_reg0
(
    .clk(clk),
	.SCLR(1'b0),
	.CLRN(rst_n),
	.D(q2),

	.Q(data_out)
);

endmodule

module DFF
(
    input    wire    clk,
	input    wire    SCLR,
	input    wire    CLRN,
	input    wire    D,

	output   reg     Q
);

always@(posedge clk or negedge CLRN)
    if (CLRN == 1'b0)
	    Q <= 1'b0;
	else
	    if(SCLR == 1'b0)
		    Q <= D;
		else if (SCLR == 1'b1)
		    Q <= 1'b0;
	    
endmodule

module and1
(
    input    wire    data1,
	input    wire    data2,

	output   wire    out
);

assign out = data1 & data2;

endmodule

写完以后看了别的大佬的写法，感觉自己太老实了。0.0