题解 | #位拆分与运算#

`timescale 1ns/1ns
 
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg valid;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
       valid <='d0;
    end
    else if(sel=='d0)begin
       valid <='d0;
    end
    else begin
       valid <='d1;
    end
end
 
assign validout = valid;
 
reg [4:0] out_data;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        out_data <='d0;   
    end
    else begin
    case(sel)
    'd0: out_data <= 0;
    'd1: out_data <= buffer[3:0]+buffer[7:4];
    'd2: out_data <= buffer[3:0]+buffer[11:8];
    'd3: out_data <= buffer[3:0]+buffer[15:12];
    default :  out_data <= 0;
    endcase
    end
end
 
  
reg [15:0] buffer;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        buffer <='d0;  
    end
    else if(sel==0) begin
        buffer <= d;
    end
    else
        buffer <= buffer;
end
 
assign out = out_data;
 
 
//*************code***********//
endmodule