题解 | #信号级联合并#

`timescale 1ns/1ns

module top_module(
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );

    wire [31:0] data ;

    assign data = {a,b,c,d,e,f,2'd3};
    assign w = data[31:24];
    assign x = data[23:16];
    assign y = data[15:8] ;
    assign z = data[7:0]  ;
endmodule