题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

reg data_in_reg;
always@(posedge clk) begin
	if(rst_n==0) begin
		data_in_reg <= 0;
	end
	else begin
		data_in_reg <= data_in;
	end
end

wire always1;
assign always1 = data_in & (~data_in_reg);

always@(posedge clk) begin
	if(rst_n==0) begin
		data_out <= 0;
	end
	else begin
		data_out <= always1;
	end
end



endmodule