题解 | #根据状态转移图实现时序电路#

三段式FSM

第一段：把次态给现态

第二段：组合逻辑，设置各个状态之间的转移条件

第三段：时序逻辑，每个状态下输出

问题，该题目第三段状态机用时序逻辑提示错误，仿真不对，为什么啊？

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg [1:0] curr_state;
reg [1:0] next_state;

localparam s0 = 2'b00;
localparam s1 = 2'b01;
localparam s2 = 2'b10;
localparam s3 = 2'b11;
//FSM the first paragraph
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        curr_state <= s0;
        next_state <= s0;
    end
    else 
        curr_state <= next_state;
end
//FSM secend paragraph
always@( *)begin
    case(curr_state)
        s0: if(C==1'b1)
                next_state = s1;
            else
                next_state = s0;
        s1: if(C==1'b1)
                next_state = s1 ;
            else
                next_state = s3;
        s2: if(C==1'b0)
                next_state = s0;
            else
                next_state = s2;
        s3: if(C==1'b1)
                next_state = s2;
            else
                next_state =s3 ;
        default:
            next_state = s0;
    endcase
end
//thrid 
reg r_Y;
always@(*)begin

    case (curr_state)
        s0: r_Y = 0;
        s1: r_Y = 0;
        s2: if(C==1)    r_Y = 1; else  r_Y = 0;
        s3: r_Y = 1;
    endcase
end
assign Y= r_Y;
endmodule