题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0]state,next_state;
always@(posedge clk or negedge rst)begin
if(!rst)begin
state<=s0;
end
else begin
state<=next_state;
end

end

always@(*)
begin
	case(state)
	s0:begin next_state=data?s1:s0;
	flag=0;
	end
	
	s1:begin next_state=data?s2:s1;
	flag=0;
	end
	
	s2: begin next_state=data?s3:s2;
	flag=0;
	end
	
	s3:begin next_state=data?s4:s3;
	flag=0;
	end
	
	s4:begin next_state=data?s1:s0;
	flag=1;
	end
	default begin
	next_state=s0;
	flag=1;
	end
	endcase
end

//*************code***********//
endmodule